1. Field of the Invention
The present invention relates generally to the field of semiconductor thin film resistors, and more particularly, to a novel integrated circuit thin film resistor having a current density enhancing layer.
2. Description of the Prior Art
In semiconductor integrated circuits (ICs), a resistor may be used to control the resistance of other electronic components of the IC. As is known to those skilled in the art, the resistance, R, of a resistor is proportional to the length, L, of the resistor and the reciprocal cross sectional area, 1 /A, of the resistor; the L and A are measured in the direction of current flow. The basic equation for resistance of a resistor is thus: R=L/A, where R, L and A are as defined above.
Prior art resistors are typically composed of polysilicon that has been doped. As the integration of semiconductor devices increases, each component within a semiconductor IC has to provide equivalent or better electrical properties. A downscaled resistor thus has to provide a constant resistance value that does not fluctuate much during use. However, due to the properties of polysilicon, a prior art resistor comprised of doped polysilicon can only provide a limited resistance within a limited space. Employing a polysilicon resistor to provide relatively high resistance then becomes a problem in designing and fabricating a highly integrated semiconductor device.
Recently, doped polysilicon resistors have been replaced with a single thin film resistor that is comprised of a material that has a higher resistivity than that of polysilicon. Examples of such higher resistivity materials include, but are not limited to: TiN and TaN. Tantalum nitride, TaN, containing 36% N2 is a material currently being used in the back-end-of-the line (BEOL) of most semiconductor devices.
BEOL resistors of high current carrying capability are highly desired by integrated circuit designers. Current TaN resistors (e.g., K1 resistor) offer only 0.5 mA/μm current/width and ever lower current density for 9SF and 10SF generations.
FIG. 1 depicts a BEOL resistor structure 10 according to the prior art. As shown, the BEOL resistor structure is formed atop of a first metallization level M1 comprising a metal such as aluminum or copper, that is electrically coupled by via structures V1, to FEOL device structures 15, e.g., CMOS FET or BJT or like transistor devices formed utilizing conventional techniques that are well known to those skilled in the art. The first metallization level M1 includes an interlevel dielectric material layer 12 in which the M1 metal layer structures are formed. As shown in the structure 10 of FIG. 1, formed atop the interlevel dielectric material layer 12 and M1 metallization is a first thin-film cap dielectric layer 14 of a material such as SiN and a thin dielectric layer 16 deposited thereon comprising an oxide, such as SiO2, or any other like oxide. The thin-film TaN resistor structure 20 of between 300 Å to 700 Å is shown formed on top of the dielectric layer 16, and a thin film capping layer, i.e., etch stop layer 25 of SiN or SiCN (nBLOK), for example, is formed over the resistor structure. Then, typical fabrication processes as known in the art are used to form a further interlevel dielectric material layer and a via structure V1 that connects the first metallization to a second metallization level M2.
For copper interconnects, better passivation and capping of the top surface of the metal has been proven to increase the electro migration performance of the copper. CoWP and reverse liner barrier films have be demonstrated to increase the performance of the interconnects. It is suspected, however, that for the TaN resistor, capping materials such as SiN or SiCN are not providing sufficient protection (and capping) for higher current performance.
Moreover, the currently provided etch stop layer, e.g., nBLOK (SiCN) or SiN, does not adhere well to the TaN film, and thus not as effective to prevent shifting of resistance during stress/aging.
U.S. Published Patent Application No. US 2004/0152299 describes a method of forming a thin film resistor. In this disclosure, a conductive layer 120 of TiN or TiW formed after the via hole (as in a linear) and a layer that comprises a typical etch stop layer (e.g., SiN). This “stack” actually is comprised of “Resistor film/SiN/Via.
U.S. Published Patent Application No. US 2004/0203192 describes methods for forming Cu lines with organic monolayers bonded to the surface for increased electro migration resistance.
It would be highly desirable to provide a novel thin film resistor structure and method of fabricating the resistor by providing a barrier material over the thin-film resistor structure to thereby enhance the current-carrying capability of the resistor.
It would be highly desirable to provide a novel thin film resistor structure and method of fabricating the resistor by providing a barrier material layer over a TaN film resistor structure that exhibits increased resistance to stress/aging.